1. Field of the Invention
The present invention relates to a semiconductor fabrication method. More particularly, the present invention relates to a method of fabricating a storage node of a capacitor.
2. Description of the Related Art
As the integration of semiconductor devices increases, sizes of semiconductor devices must be decreases in accord with a design rule. However, as the size of a DRAM (dynamic random access memory) decreases, the capacitance of a DRAM capacitor is correspondingly reduced. Therefore, it is necessary to refresh the capacitor frequently. In order to decrease the refreshing frequency, the capacitance of the capacitor must be increased. Methods for increasing the storage capacitance of the capacitor include (1) increasing the surface area of a capacitor; (2) selecting a dielectric material with a high dielectric constant; and (3) reducing the thickness of a dielectric layer. Because of the limitation in dielectric materials and fabrication techniques, only limited reduction can be made in the thickness of the dielectric layer.
An electrode with a hemispherical grained silicon (HSG-Si) layer with increased surface area is commonly used in a storage electrode for increasing the capacitance of a capacitor. Since the HSG-Si layer is formed at a high temperature, an out-gassing problem easily occurs in an inter-poly dielectric (IPD) layer. The gas generated from the IPD layer easily is easily adsorbed to the surface of the storage electrode and retards the silicon migration of the storage electrode. Thus, the formation of the HSG-Si layer the storage electrode is suppressed. The conventional method solves the out-gassing problem by forming a silicon nitride layer on the IPD layer. However, this causes a poor etching selectivity during the formation of the hemispherical grains. That is, silicon atoms also migrate on a surface of the silicon nitride layer to affect the insulation performance of the IPD layer.